1. Field of the Invention
The present invention relates generally to electronic packaging technology and, more particularly, to a bumped chip carrier package using a lead frame.
2. Description of the Related Art
Like other sectors of the semiconductor industry, the electronic packaging industry strives for packages that are smaller, lighter, faster, more multi-functional, higher performance, and more reliable. A chip size package (CSP) satisfies the industry's demand for the smallest form factor, thereby allowing smaller and advanced electronic end-applications.
A typical CSP is a bumped chip carrier (BCC) package as disclosed in U.S. Pat. No. 6,573,121. As illustrated in the above patent, a conventional BCC package includes a resin package sealing a semiconductor chip, and resin projections protruding from a surface of the resin package. Furthermore, a metallic film is plated on the resin projections and electrically connected to the semiconductor chip via bond wires. The resin projections plated with the metallic film act as terminals for external connection. Since the height of the external terminals may be adjustably controlled during the manufacture, the conventional BCC package may have an advantage over other types of CSPs using solder balls as external terminals.
Unfortunately, the metallic plating film may crack due to a difference in the coefficient of thermal expansion between the metallic film and the resin projections during reliability tests such as a temperature cycling test. Another drawback of the conventional BCC package is that the wire bonding process requires a two-step ball bonding operation. Specifically, the bond wires are ball-bonded to the metallic film as well as the chip, in comparison with a general wire bonding technique composed of a stitch bonding and a ball bonding.
A technique to solve the above-discussed problems has been introduced by the Applicant, which is disclosed in U.S. Patent Publication No. 20030015780. FIG. 1 illustrates a conventional BCC package 50 disclosed in the above Publication. Referring to FIG. 1, since a solder layer 16 is formed on a lead frame 19 used as a frame for external terminals 18, the external terminals 18 may be prevented from being damaged during reliability tests. Additionally, bond wires 21 can be stitch-bonded to inner sides of the lead frame 19 used as internal terminals 14, requiring only a one-step ball bonding operation.
Such a structure, however, has a drawback that the solder layer 16 has a poor adhesive strength to the lead frame 19. Unfortunately, this may invite the lowering of solder joint reliability and may result in delamination and/or cracking between the solder layer 16 and the lead frame 19 when the BCC package 50 is mounted on a next-level circuit board through solder balls produced by reflowing the solder layer 16.
Therefore a need remains to obviate and mitigate at least some of the above-mentioned disadvantages.